• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to an MML semiconductor device, particularly comprising forming a silicide layer in a source / drain region of a logic gate electrode; Stacking a first interpoly oxide film on the entire surface of the DRAM region and the logic region with a predetermined thickness; After the step of forming a first contact hole on the first interpoly oxide film having a first photoresist film having a first contact portion as a logic region and then etched to open the silicide layer of the logic gate electrode; Stacking a metal layer in the first contact hole and etching to form a lower metal wiring; Stacking a second interpoly oxide film over the entire region of the resultant, and then laminating a second photoresist film having a second contact portion at a position of a DRAM region and a lower metal wiring of a logic region thereon; Etching a lower oxide layer through the second contact portion to form a DRAM contact hole and a second logic contact hole; A method of manufacturing an MML semiconductor device comprising: forming a metal layer through the DRAM contact hole and the second logic contact hole and forming a logic metal wiring connected to the DRAM metal wiring and the lower metal wiring by etching. By forming a contact hole in the logic region to form a metal wiring in the second step, it is a very useful and effective invention to prevent damage to the silicide layer of the logic region and to accurately and easily form the metal wiring.
    公开号:KR20000004745A
    申请号:KR1019980026241
    申请日:1998-06-30
    公开日:2000-01-25
    发明作者:문원；윤치성
    申请人:김영환；현대전자산업 주식회사；
    IPC主号:
    专利说明:

    MML Semiconductor Method
    The present invention relates to an MML semiconductor device, and more particularly, to form a silicide layer by opening a transistor in a logic region, and then forming a lower metal wiring by using a first contact hole in a logic region using a photosensitive film, and then stacking an oxide layer. The present invention relates to an MML semiconductor device manufacturing method for forming a contact hole in a DRAM region and a logic region and stacking metal interconnects therein, thereby preventing damage to the silicide layer of the logic region and facilitating formation of the metal interconnection.
    In general, a mixed semiconductor (MML: Merged Memory Logic), in which memory and logic are formed on a single chip, has been increasingly used in recent years, and this MML semiconductor device has been increasingly used. Since it is possible to manufacture a single process in one chip and memory, it has the advantage that it can operate at a higher speed and use at lower power than existing chips without any special design change.
    On the other hand, since the manufacturing process of the memory product and the manufacturing process of the logic product are manufactured on the same chip at the same time, the size of the unit chip is increased, and therefore, it has a disadvantage that requires a lot of difficulty to proceed with the manufacturing process. Transistors have more emphasis on preventing leakage current than requiring high current driving force, but logic products must be manufactured on one chip with both characteristics such as high current driving capability.
    As described above, in the semiconductor substrate, a field oxide film and a gate electrode of a transistor are simultaneously formed in a memory region and a logic region, a spacer film is stacked on a side portion of the gate electrode, and ions are implanted into an active region to form a source / drain. After the process, a capacitor was formed on the field oxide film of the memory region by a high temperature process of 800 ° C., and the insulating layer and the metal wiring layer of the oxide film were formed on the transistor of the logic region and the transistor and capacitor of the memory region. Lamination is carried out in a multilayer process.
    By the way, as described above, the transistors in the memory region place emphasis on the prevention of leakage current, while the transistors in the logic region place emphasis on having a high current driving capability. After the formation of all, the process of manufacturing a high temperature capacitor (about 800 ℃) in the memory region is performed, which is important for transistors already manufactured in the logic region, particularly for silicide layers formed in the source / drain and active regions of the transistor. In this case, the current driving ability of the transistor in the logic region is lowered, thereby degrading the performance of the device.
    In addition, since a transistor and a capacitor are formed in the DRAM area, which serves as a memory, and only a transistor is formed in the logic area, only a transistor is formed on the same chip to increase the height of the DRAM area. Due to the height of the capacitor, the process of forming a subsequent contact has a problem in that an accurate contact cannot be formed because a considerable deep contact is formed due to a high aspect ratio.
    An object of the present invention is to form a silicide layer by opening a transistor in a logic region by forming a capacitor in the DRAM region and then etching the insulating film stacked in the DRAM region and the logic region to form a silicide layer, and then using the photosensitive film to form a first contact hole in the logic region. The lower metal wiring wiring is formed by using, and the oxide film is stacked again to form contact holes in the DRAM region and the logic region, and the metal wiring is laminated therein, thereby preventing damage to the silicide layer of the logic region and forming the metal wiring. The purpose is to facilitate.
    1 to 9 (a) is a view sequentially showing a method of manufacturing an MML semiconductor device of an embodiment of the present invention,
    1 to 9 (b) is a view sequentially showing a manufacturing method of MML semiconductor device according to another embodiment of the present invention.
    * Description of the symbols for the main parts of the drawings *
    10: semiconductor substrate 15: field oxide film
    20: DRAM gate electrode 25: logic gate electrode
    30 capacitor 35 insulation film
    40: silicide layer 45: first interpoly oxide film
    50: first photosensitive film 55: first contact portion
    60,60 ': Metal wiring 70,70': Second photosensitive film
    75,75 ': Second contact area 80,80': DRAM metal wiring
    85,85 ': Logic metal wiring
    The purpose of the present invention is to form a DRAM gate electrode and a capacitor in the DRAM region, and a logic gate electrode in the logic region, and then, depositing an insulating film over the entire region; Removing a portion of the logic region from the insulating film to open the logic gate electrode, and then forming a silicide layer in the source / drain region; Stacking a first interpoly oxide film on the entire surface of the DRAM region and the logic region with a predetermined thickness; After the step of forming a first contact hole on the first interpoly oxide film having a first photoresist film having a first contact portion as a logic region and then etched to open the silicide layer of the logic gate electrode; Stacking a metal layer in the first contact hole and etching to form a lower metal wiring; Stacking a second interpoly oxide film over the entire region of the resultant, and then laminating a second photoresist film having a second contact portion at a position of a DRAM region and a lower metal wiring of a logic region thereon; Etching a lower oxide layer through the second contact portion to form a DRAM contact hole and a second logic contact hole; It is achieved by providing a method of manufacturing an MML semiconductor device comprising the step of forming a logic metal wiring connected to the DRAM metal wiring and the lower metal wiring by laminating a metal layer through the DRAM contact hole and the second logic contact hole. The method may further include a process of depositing the second interpoly oxide film and then planarizing the thickness, wherein the thickness of the first interpoly oxide film is 1 μm or less, and the lower metal wiring, the DRAM metal wiring, and the logic metal wiring are metal layers. Is formed by an etch back process after deposition by CVD method. The insulating film is also achieved by providing an MML semiconductor device for exposing a logic gate electrode by wet etching or dry etching.
    Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
    1 shows a DRAM gate electrode 20 and a capacitor 30 formed in a DRAM region a, and a logic gate electrode 25 formed in a logic region b, and then an insulating film 35 is stacked on all regions. The state is shown.
    2 is a state in which the silicide layer 40 is formed in the source / drain region after opening the logic gate electrode 25 by removing a portion of the logic region b by wet etching or dry etching in the middle of the insulating layer 35. It is shown.
    3 illustrates a state in which the first interpoly oxide film 45 is laminated on the entire surface of the DRAM region a and the logic region b, in particular, having a thickness of 1 μm or less.
    FIG. 4 illustrates a state in which the first photoresist film 50 having the first contact portion 55 is stacked in the logic region b on the first interpoly oxide film 45 after the step.
    FIG. 5 illustrates a state in which a first contact hole 47 is opened to the silicide layer 40 of the logic gate electrode 25 by etching through the first contact portion 55 after the step.
    FIG. 6A illustrates a state in which a lower metal wiring 60 is formed by stacking and etching a metal layer in the first contact hole 47.
    FIG. 7A illustrates the planarization process of stacking the second interpoly oxide film 65 over the entire region of the resultant material, and planarizing the second interpoly oxide film 65 on the lower metal wiring 60 of the DRAM region a and the logic region b. The state in which the second photosensitive film 70 having the second contact portion 75 is laminated is shown.
    FIG. 8A illustrates a state in which a DRAM contact hole 67 and a second logic contact hole 69 are formed by etching a lower oxide layer through the second contact portion 75.
    9A illustrates a logic metal connected to the DRAM metal wiring 80 and the lower metal wiring 60 by etching after stacking a metal layer through the DRAM contact hole 67 and the second logic contact hole 69. The state which forms the wiring 85 is shown.
    The lower metal interconnection 60, the DRAM metal interconnection 80, and the logic metal interconnection 85 may be formed by an etch back process after depositing a metal layer by a chemical vapor deposition (CVD) method.
    And, with reference to the accompanying drawings will be described in detail for another preferred embodiment of the present invention.
    Meanwhile, in the case of other embodiments, the same steps are applied to the processes of FIGS. 1 to 5, and thus descriptions thereof will be omitted. Referring to the cases of FIGS. 6 (b) to 9 (b), the first contact holes 47 are formed. The lower metal wiring 60 'is etched without being exposed to the upper portion, and after the second interpoly oxide film 65' is stacked thereon, the second contact portion 75 'of the second photoresist film 70'. Etching to form the DRAM contact hole 67 'and the second logic contact hole 69', and laminating a metal layer to form the DRAM metal wiring 80 'and the logic metal wiring 85' through etching. The state of doing is shown.
    As described above, when the MML semiconductor device manufacturing method according to the present invention is used, a capacitor is formed in a DRAM region by a high temperature process, and then an insulating film stacked on the DRAM region and the logic region is etched to open the transistor in the logic region to open the silicide. Forming the layer prevents damage to the silicide layer of the logic region due to the high temperature thermal process of the capacitor in the DRAM region, and also forms the lower metal wiring in one step by using the first contact hole in the logic region using the photosensitive film. Since the oxide film is stacked to form contact holes in the DRAM region and the logic region, and the metal wiring is stacked in the second step, it is a very useful and effective invention to accurately and easily form the metal wiring.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] Forming a DRAM gate electrode and a capacitor in the DRAM region, and forming a logic gate electrode in the logic region, and then stacking insulating films over the entire region;
    Removing a portion of the logic region from the insulating film to open the logic gate electrode, and then forming a silicide layer in the source / drain region;
    Stacking a first interpoly oxide film on the entire surface of the DRAM region and the logic region with a predetermined thickness;
    After the step of forming a first contact hole on the first interpoly oxide film having a first photoresist film having a first contact portion as a logic region and then etched to open the silicide layer of the logic gate electrode;
    Stacking a metal layer in the first contact hole and etching to form a lower metal wiring;
    Stacking a second interpoly oxide film over the entire region of the resultant, and then laminating a second photoresist film having a second contact portion at a position of a DRAM region and a lower metal wiring of a logic region thereon;
    Etching a lower oxide layer through the second contact portion to form a DRAM contact hole and a second logic contact hole;
    And stacking a metal layer through the DRAM contact hole and the second logic contact hole, and forming a logic metal wiring connected to the DRAM metal wiring and the lower metal wiring by etching.
    [2" claim-type="Currently amended] The MML semiconductor device manufacturing method of claim 1, further comprising planarizing the second interpoly oxide layer and depositing the second interpoly oxide film.
    [3" claim-type="Currently amended] The method of claim 1, wherein the thickness of the first interpoly oxide film is 1 µm or less.
    [4" claim-type="Currently amended] The method of claim 1, wherein the lower metal wiring, the DRAM metal wiring, and the logic metal wiring are formed by an etch back process after depositing a metal layer by CVD.
    [5" claim-type="Currently amended] The method of claim 1, wherein the insulating film exposes the logic gate electrode (25) by wet etching or dry etching.
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    同族专利:
    公开号 | 公开日
    KR100475715B1|2005-05-27|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-06-30|Application filed by 김영환, 현대전자산업 주식회사
    1998-06-30|Priority to KR10-1998-0026241A
    2000-01-25|Publication of KR20000004745A
    2005-05-27|Application granted
    2005-05-27|Publication of KR100475715B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR10-1998-0026241A|KR100475715B1|1998-06-30|1998-06-30|Mml semiconductor device manufacturing method|
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